Awesome ASIC design verification
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Feb 9, 2022
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asic-verification
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IC implementation of Systolic Array for TPU
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Oct 21, 2024 - Verilog
VIP for AXI Protocol
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May 24, 2022 - SystemVerilog
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus
python c fpga cpp processor vhdl logic verification dpi verilog systemverilog pli vpi codesign simulation-element asic-verification logic-simulation dpi-c cosimulation vhpidirect
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Feb 12, 2026 - VHDL
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be ...
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Dec 3, 2023 - Verilog
A custom AI chip to be taped out soon!
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Dec 20, 2025 - Python
Quasar 2.0: Chisel equivalent of SweRV-EL2
scala processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2
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Apr 13, 2021 - Scala
Hdl is a tool for easing the work with hardware description languages.
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Dec 12, 2022 - Go
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification
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Nov 16, 2024 - SystemVerilog
The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
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May 6, 2023 - VHDL
Application Specific Integrated Circuit(ASIC)
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Jun 7, 2018 - SystemVerilog
Made Million Instruction Per Second Processor
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Feb 24, 2018
UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)
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Jun 24, 2025 - SystemVerilog
End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.
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Mar 26, 2025 - Verilog
Scalable UVM Testbench for a 4-Agent router. Implements Virtual Sequencers, RAL, multi-port Scoreboarding, Functional Coverage, and DPI-C Golden Model.
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Feb 11, 2026 - SystemVerilog
VHDL implementation of an "asynchronous" FIFO with 64 positions of 8-bit words. Features dual clock domains (wr_clk, rd_clk), asynchronous reset, status signals (empty, full, almost empty/full, error), testbench, synthesis scripts, and timing/power/area reports.
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Jul 16, 2025 - VHDL
SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).
dsp systemverilog soc uvm risc-v genus riscv32 asic-verification axi4 axi4-lite axi4-protocol asic-design xcelium neorv32 uvm-verification innovus cadence-xcelium axi4-lite-system-verilog uvm-testbench genus-synthesis
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Feb 5, 2026
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