A bunch of MIPS (assembly) programming exercises and problems done in college as a part of the course Computer Architecture (CS F342).

• Updated Nov 26, 2019
• Assembly

Compilation of my Computer Architrcture and Verilog Courses at UW. Documentation for the code included in the individual directories.

• Updated Feb 14, 2023
• Verilog

[ECE NTUA] Computer Architecture class 2016 - 2017

• Updated Feb 20, 2017
• Assembly

32-bit 5-stage pipelined RISC-V CPU (RV32I) in Verilog HDL. Supports ADD, SUB, AND, OR, LW, SW, BEQ, BNE with hazard handling (forwarding, stalls, flushes). Verified using testbenches and GTKWave, achieving CPI 1.0 on hazard-free execution.

• Updated Sep 24, 2025
• Verilog

Nand2Tetris - Building a simulated Computer System from First Principle

• Updated Oct 21, 2018
• Assembly

ENGR3410 PDFs

• Updated May 14, 2017

Lab assignments and some practise done for the Computer Architecture course at BITS Pilani

• Updated Nov 10, 2019
• Verilog