axi-stream

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

fpga udp verilog axi-stream

Updated Mar 15, 2022
Verilog

fcayci / vhdl-axis-uart

Star 18

UART to AXI Stream interface written in VHDL

fpga vhdl uart axi-stream

Updated Oct 20, 2022
VHDL

DOUDIU / AXIS-AXI4-AXIS

Star 12

This project is designed to delay the output of the video stream in AXI-STREAM format.

fpga ddr axi-stream axi-full

Updated Jul 14, 2024
Verilog

catarinaacsilva / vivado-xilinx-tutorials

Star 7

Tutorials or projects example to use Vivado 2019.2 and Vitis

fpga hardware timer software rtos axi-dma memory-mapped axi-stream

Updated Oct 27, 2020
VHDL

ShoukathAli23 / Image-Video-Processing-on-FPGA

Star 6

Various video processing projects will be shared here

fpga vhdl image-processing video-processing pynq-z1 axi-stream

Updated May 26, 2020
Jupyter Notebook

gururavi / rtl

Star 5

Synchronous and Asynchronous FIFO with AXI interface

fpga pipeline rtl synthesis systemverilog fifo axi floating-point-arithmetic axi-stream axi4

Updated Nov 20, 2019
SystemVerilog

MasterPlayer / axis_uart_bridge

Star 5

FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol

fpga zynq xilinx uart systemverilog artix uart-tx axi-stream uart-rx

Updated Dec 2, 2021
SystemVerilog

amamory / axis-skidbuffer

Star 4

A one-position buffer compatible with AXI Stream interface

vivado axi-stream skidbuffer

Updated May 23, 2023
Tcl

pkill37 / fpga-gradient-descent

Star 4

FPGA benchmark of vectorized gradient descent on linear regression

fpga linear-regression vhdl xilinx gradient-descent microblaze axi axi-stream

Updated Aug 13, 2018
VHDL

amamory / axis-skidbuffer-lfsr

Star 3

An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals

vivado lfsr axi-stream skidbuffer

Updated Aug 10, 2020
Tcl

MasterPlayer / adxl345-sv

Star 3

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

fpga zynq i2c adxl345 systemverilog interrupts axi-stream axi-lite

Updated Feb 20, 2023
C

aryan-programmer / axi_gen_and_sum_primes_fpga

Star 3

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

embedded fpga hls xilinx vivado xilinx-fpga basys3 xilinx-vivado axi artix axi-stream vivado-ip-integrator artix-7 xilinx-hls vitis axi-lite xilinx-vitis vivado-vitis vitis-hls axi-memory-mapped

Updated Nov 21, 2023
TeX

amamory / axis-protocol-checker

Star 2

AXI stream protocol checking design

vivado zynq-7000 axi-stream axi4

Updated Aug 9, 2020
Tcl

mnemocron / axi-perf-counter-pattern

Star 2

Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.

vhdl performance-analysis axi-bus axi-stream axi4 latency-analysis

Updated Aug 3, 2023
VHDL

aryan-programmer / axi_stream_array_sum_microblaze

Star 2

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.