Affordable 2 GHz 3.2 GS/s 12 bit open-source open-hardware expandable USB real-time oscilloscope
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Feb 24, 2026 - FIRRTL
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altera-fpga
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Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
fpga verilog logic-analyzer xilinx-fpga altera-fpga lattice-fpga digital-signal-analyzer ftdi232h ftdi2232h
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Jun 24, 2021 - Verilog
Verilog code to replace the Commodore SDMAC found in the A3000
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Feb 6, 2026 - Verilog
SoCFPGA: Mapping HPS Peripherals, like I2C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto
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Jun 9, 2021 - Verilog
Tou Guo Shu Wei Luo Ji Jie He VHDLYu VerilogDe Guo Cheng ,Zuo Wei Cong Ji Chu Shu Wei Luo Ji Dao Ji Suan Ji Xi Tong Jie Gou ,Bing Shi Zuo Chu Yi Ke CPUDe Jiao Xue Shu Ji ,Xi Wang Wei Lai Ke Yi Cheng Wei Jiao Xue Fan Li Dang An . Mu Qian Jiang Kai Fa Zhuan Yi Dao GitLab,Yin Wei Ke Yi Cheng Xian Shu Xue Yu MULTu .
fpga digital vhdl verilog learn xilinx digital-logic systemverilog hdl verilog-hdl xilinx-fpga xilinx-vivado digital-logic-design altera-fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 altera-quartus soc-kit altera-cyclone vhdl-verilog
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Oct 25, 2023 - Verilog
VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls
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Dec 17, 2019 - VHDL
This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.
fpga electronics vhdl stm32 embedded-systems modelsim quartus-prime altera-fpga rtl-design-and-verification
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Jan 27, 2026 - C
This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.
fpga riscv altera ucberkeley risc-v altera-fpga riscv-asm de10-nano riscv64 terasic rocketchip riscv-assembly chipyard
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Feb 7, 2022 - Verilog
FPGA implementation of the popular logic game using VHDL and Altera DE1
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Apr 21, 2018 - VHDL
Graph Processing Framework that supports || OpenMP || CAPI
accelerator pagerank dfs benchmarking-suite ibm systemverilog bfs spmv capi betweenness-centrality triangle-counting graph-framework fgpa connected-components graph-algorithm altera-fpga sssp ibm-capi accelgraph-capi opencapi
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Jan 21, 2023 - SystemVerilog
Research & Development FPGA projects for different boards
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Oct 1, 2023 - GLSL
Implementation of an Edge Detection Filter Using the Avalon Interface
fpga verilog edge-detection avalon sobel quartus altera-fpga sobel-filter rgb2gray sobel-edge-detector avalon-bus avalon-streaming
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Jan 30, 2023 - Verilog
Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.
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Apr 25, 2019 - Verilog
An 8-bit processor in VHDL based on a simple instruction set
processor-architecture fpga processor vhdl verilog vivado hardware-designs hdl xilinx-fpga processor-simulator hardware-description-language digital-electronics altera-fpga processor-design
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Mar 7, 2019 - VHDL
Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract
fpga hardware signal-processing verilog sdr altera digital-signal-processing digital-design dcf77 dcf-decoder altera-fpga
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May 22, 2018 - Verilog
This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).
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Oct 26, 2019 - SystemVerilog
FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA
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Nov 21, 2022 - Verilog
This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.
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Feb 5, 2025 - Verilog
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