Single Cycle RISC-V Processor Implemented on FPGA
Project Overview
This project implements a Single-Cycle RISC-V Processor using SystemVerilog on a Nexys A7 (Artix-7) FPGA. Project includes complete datapath and control logic with instruction memory, data memory, ALU, immediate generator, and branch comparator. It supports the complete RV32I instruction set (R, I, S, B, U, J types) and is optimized for educational clarity and hardware-software co-design learning.
Tools & Technologies
| Type | Tool/Tech |
|---|---|
| Hardware | Nexys A7 FPGA (Artix-7, Digilent) |
| Language | SystemVerilog (HDL) |
| Software | Xilinx Vivado (Simulation + Synthesis) |
| Extras | RISC-V Assembly, .mem files for memory preloading |
Key Features
- Single-Cycle Execution
Executes one complete RISC-V instruction per clock cycle, enabling straightforward control logic and easier debugging. - Modular Design
Each processor component (ALU, Control Unit, Register File, etc.) is developed as a reusable SystemVerilog module. - Full RV32I Support
Supports all 32-bit base integer instruction types: R, I, S, B, U, and J. - Immediate Decoding & Sign Extension
Fully functional Immediate Generator for all instruction formats with correct 32-bit sign-extension. - Memory Preloading
Instruction memory, data memory, and register file can be initialized via.memfiles for controlled simulation. - Simulation Verified
All components tested with custom SystemVerilog testbenches in Xilinx Vivado simulator. - RTL & Timing Diagrams
Visual representation of RTL structure and timing behavior captured using Vivado tools. - Synthesizable for FPGA
Fully synthesizable and deployed on the Digilent Nexys A7 board (Artix-7 FPGA) without timing violations. - Educational Focus
Designed to offer clarity and transparency in digital design, ideal for students learning computer architecture and hardware design.
System Architecture
Each instruction follows 5 basic stages in one cycle:
- Fetch
- Decode
- Execute
- Memory Access
- Write Back
Key Components
Datapath and Control path
Implementation
Testing and Results
RTL Diagrams
These RTL (Register Transfer Level) views were auto-generated using Xilinx Vivado. They illustrate the structural connectivity and module instantiations within the design.
RTL schematic of the Top Module
RTL schematic of the Control Unit Module
RTL schematic of the Instruction Memory Module
RTL schematic of the Branch Comparator Module
RTL schematic of the Immediate Generator Module
RTL schematic of the Register File Module
RTL schematic of the Program Counter Module
RTL schematic of the ALU Logic Module
RTL schematic of the Data Memory Module
Timing Diagrams
Timing diagrams were extracted from Vivado simulations to validate functional behavior.
Timing diagrams of Top Module:
Timing diagrams of Control Unit Module
Timing diagrams of Instruction Memory Module
Timing diagrams of Branch Comparator Module
Timing diagrams of Immediate Generator Module
Timing diagrams of Program Counter Module
Timing diagrams of Register File Module
Timing diagrams of ALU Logic Module
Timing diagrams of Data Memory Module
Simulation Outputs
These snapshots show the overall system execution for a sample RISC-V program.
Project Folder Structure
Conclusion
Future Enhancements
License
This project is licensed under the MIT License.
Author
Awais Asghar
NUST Chip Design Centre
