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Summary

DescriptionISA Bus pins.svg
English: Schematic illustration of the pins of an ISA Bus slot.
Date
Source
Author Fred the Oyster
SVG development
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This vector image was created with Adobe Illustrator.

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Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled GNU Free Documentation License.http://www.gnu.org/copyleft/fdl.htmlGFDLGNU Free Documentation Licensetruetrue

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5 November 2014

32,734 byte

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5c5d07fcba846ca028b18e6a566e00362bec7079

File history

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Date/TimeThumbnailDimensionsUserComment
current04:59, 28 November 2019970 x 1,537 (32 KB)Rasz plIRQ 2 typo
19:15, 1 December 2016970 x 1,537 (32 KB)Rasz plB18 corrected to "DRQ1", B8 corrected to "/0WS" or "/No WaitState" or "/Zero Waitstate" as per IBM PC/AT Technical Reference Manual (pg 1-27) "0WS (I) The 'Zero Wait State' (0WS) signal tells the microprocessor that it can complete the present bus cycl...
16:37, 5 November 2014970 x 1,537 (32 KB)Fred the Oyster{{Information |Description ={{en|1=Schematic illustrations of the pins of an ISA Bus slot}} |Source =100px |Author =Fred the Oyster
{{Adobe|v}} |Date =2014-11-05 |Permi...

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Width970px
Height1537px